Measurement Data for "An Analysis of Energy Efficiency Features in Intel Sapphire Rapids Processors"
Documentation of the data | The folders in the data follow the format: 'System Name'/'Experiment Name'/'Experiment Time'. Each of the folder contains a git-tag which describes the version of the experiment, the parameters of the booted kernel and its loaded modules, the hwloc topology and lshw output. This facilitates interpretability and reproducibility of the measurement data. | |
References to related material | Diploma thesis: Schmidl, M. (2025). An Analysis of Energy Efficiency Features in Intel Sapphire Rapids Processors. | |
References to related material | https://github.com/marenz2569/2025-sappire-rapids-ee | |
Type of the data | Dataset | |
Total size of the dataset | 39561026435 | |
Author | Schmidl, Markus | |
Upload date | 2025-12-02T15:06:35Z | |
Publication date | 2025-12-02T15:06:35Z | |
Data of data creation | 2025 | |
Publication date | 2025-12-02 | |
Abstract of the dataset | This dataset contains performance measurement data which is used to classify internal mechanisms and characteristics that facilitate the tuning of energy efficiency on the Intel Sapphire Rapids processor generation. The data is generated from measurement configurations and code hosted at the following git repository: https://github.com/marenz2569/2025-sappire-rapids-ee | |
Public reference to this page | https://opara.zih.tu-dresden.de/handle/123456789/1715 | |
Public reference to this page | https://doi.org/10.25532/OPARA-935 | |
Publisher | Technische Universität Dresden | |
Specification of the discipline(s) | 4::44::409::409-07 | |
Title of the dataset | Measurement Data for "An Analysis of Energy Efficiency Features in Intel Sapphire Rapids Processors" | |
Project abstract | In High Performance Computing, computational throughput is used as a key system metric. Energy efficiency is, however, an equally important metric for scaling out workloads. The 4th Generation Intel Xeon Scalable Processor, codenamed Sapphire Rapids, features numerous improvements and new hardware control loops designed to optimize energy efficiency. Little information is publicly disclosed so far, leading to a lack of knowledge about these improvements. Information about the internals of these mechanisms is, however, a prerequisite to tune systems for improved energy efficiency. This thesis highlights found changes in internal control mechanisms. Key findings include qualitative and quantitative descriptions of the core and uncore frequency transitions, improvements in turbo frequencies and their allocation to cores, an evaluation of the internal power measurements, changed sleep wakeup latencies, and a description of the core microarchitecture. Moreover, I present a model to improve core to core communication latencies that result from the 2d-mesh design of the L3 cache. | |
Project title | An Analysis of Energy Efficiency Features in Intel Sapphire Rapids Processors |
Files
License bundle
1 - 1 of 1
No Thumbnail Available
- Name:
- license.txt
- Size:
- 4.66 KB
- Format:
- Item-specific license agreed to upon submission
- Description: